From An Idea To Write An Excellent Process Essay

How to write a proposal for level b2

The switching memory, is intended for switching of entrance channels (the data recording is kept consistently, and reading happens according to the card of switching), along with switching there is a temporary consolidation of the entering group channels. For alignment existence of three memories of switching is provided, when filling one of them with information of several (not all) channels filling of the following, etc. automatically begins.

Let's enter concept of a switching element. The switching element is a set of a memory of the address and the RAM of a memory of switching, the function chart of a switching element is presented in drawing 1 Scheme of the BLOCK of CYCLIC ALIGNMENT AND SWITCHING contains twenty four switching elements, i.e. on three on each of the entering group channels.

In the record mode (Rz/sch = the multiplexer connects the senior 5 categories of the counter of the address to the decoder of columns, 3 younger categories of the counter are connected to the decoder of lines. The STORAGE in this mode has the digit organization.

For implementation of switching it is necessary to create the general, condensed in time channel, and to rearrange impulses from one temporary position in another. As it was noted above technically such shift easily to execute in a memory if to write down information of the general channel consistently, and to read out according to the card of switching.

For calculation of capacity of each of two elements of memory it is necessary to find out the principle of operation of the block. At the time of record on the parallel tire eight categories of one of channels are transferred, therefore, the RAM has to contain eight elements in a column. At the time of reading eight proceeding group channels are formed, eight bits, on one on each canal come to each timepoint on an exit; therefore, the RAM has to contain eight columns. Thus, the general capacity of the RAM makes:

The RAM organization dictionary, but at a data recording each cell of memory consists of the elements of memory entering the corresponding column of a matrix, and when reading - of the elements entering the corresponding line. The function chart of this device is presented in figure 16, it consists from:

The generator of pulse sequence develops a certain set of the pulse sequences used for management of work of functional knots of the switchboard, their synchronization. At its exit three groups of impulses are developed: digit, channel and cyclic.

Let's consider the principle of cyclic alignment of the entering group channels, it consists in record in a memory of information of the entering group channels synchronously with the allocated clock impulses and their reading synchronously with station impulses of clock and cyclic synchronization.

In the reading mode (= the multiplexer connects Rz/sch to the decoder of the ZUA columns, and the decoder of lines thus is switched-off and the RAM gets the dictionary organization each of eight elements of memory of the columns of a matrix of memory which are a part form a cell of memory and are read out in parallel.

The BLOCK of FORMATION of the PROCEEDING GROUP CHANNELS, is intended for formation of 8 channels of the IKM standard - 30/32 of arriving on its entrance condensed in time and the commutated channel carried in space. For ensuring continuous formation of channels the block needs two memories, to each timepoint from one there is a reading, and to another there is a record. The block diagram of such block is submitted in figure 1

The memory of the address has the dictionary organization, both at a data recording, and when reading (one word possesses word length of 6 bits). The function chart of this device is presented in figure 1

Structurally the scheme of a memory of switching can be presented in the form of eight RAMS with a capacity of 256 bits everyone which exits are united by the general parallel tire, and on entrances of each of the RAM the respective group canals and the allocated clock impulses arrive. Such scheme is submitted in drawing